A generalized true per-pin test system is illustrated in FIG. 1. The per-pin test system has substantially identical circuitry dedicated to each of a plurality (n) of test pins to process test data going to a Device Under Test (DUT) and coming from the DUT. The system includes test pattern generating electronics, also referred to as a pattern generator, and test pin electronics for coupling to the DUT. The DUT may be, by example, an integrated circuit provided on a wafer comprising a plurality of identical circuits. The DUT may also be an integrated circuit provided on a wafer that comprises a plurality of dissimilar types of circuits. The DUT may also be a partially packaged integrated circuit having been previously scribed from the wafer. A controller, typically a data processor, is coupled to the test system through an interface for controlling the operation thereof.
Examples of per-pin test systems are described in a journal article "250-MHZ Advanced Test Systems", IEEE Design & Test of Computers, pps. 24-35, 1988 by A. J. Gruodis and D. E. Hoffman Additionally, reference is made to the following publications: Y. E. Chang, D. E. Hoffman, A. J. Gruodis, J. E. Dickol, "A 250 MHz Advanced Test System", Proceedings of International Test Conference", September 1987, pp. 68-75; J. M. McArdle, "A 250 MHz Advanced Test System Software", Proceedings of International Test Conference, September 1987, pp. 85-93; and L. Grasso, C. E. Morgan, M. S. Peloquin, F. Rajan, "A 250 MHz Test System Timing and Auto Calibration", Proceedings of International Test Conference, September 1987, pp. 76-84. Some commonly assigned U.S. Patents that disclose aspects of test systems include U.S. Pat. No. 4,639,919, Jan. 27, 1987 and U.S. Pat. No. 4,608,706, Aug. 26, 1986.
In a true per-pin test system, there are identical sets of pattern generator and test pin electronics provided for each of the tester system pins. In most, if not all, embodiments it is advantageous to physically divide the test system into a pattern generator module and into a pin electronics module, wherein the pin electronics module is disposed closely adjacent to the DUT to minimize signal delays and is electrically interconnected by cables to the typically much larger pattern generator module. The pattern generator module stores the test pattern control data, processes the outgoing test data, performs algorithmic test pattern generation, and processes the data that returns from the pin electronics module. The pin electronics module receives the test data and converts the data into electrical signals that interface through a plurality of test pins to the DUT. The pin electronics module in operation performs a number of subsidiary tasks including (a) varying a logical value, format and functional mode of the applied test data on a per-pin basis, (b) varying voltage levels sent to or expected from the DUT on a per-pin basis, and (c) varying the signal edge timings of the pin on a per-pin basis.
In high performance and high accuracy semiconductor device test systems such per-pin control is highly desirable and provides several advantages. For example, even small variances between a pin's wiring and electronics may cause unacceptable degradations in the signal quality or timing. Although care is given to the design of test systems to minimize per-pin differences and circuitry is also often included to match separate sets of pin electronics, in high performance test systems these approaches still do not guarantee a required level of uniform performance from pin to pin. Presently known types of test systems furthermore have only a relatively small set of selectable fixed signal timings, thereby limiting the number of conditions that can be specified. Also, many test systems have only a limited number of available voltage levels, thereby limiting the range and choice of voltages.
Thus, although a highly flexible per-pin specification capability is necessary to maintain a uniformity of test stimuli amongst a possibly large number of test pins, known types of test systems do not provide an adequate per-pin test specification capability that satisfactorily overcomes the tester deficiencies resulting from pin variability and other related problems. One reason for this lack of pin programmability is related to the required physical separation of the pin electronics module and the pattern generator electronics module. In that it is practical to provide only a relatively few interconnections between the modules for each pin, only a corresponding limited number of pin states can therefor be specified. The tendency of modern testers to increase the number of test pins further limits the number of per-pin interconnects that can be provided.
Also, many conventional test systems, in order to make a change in format, timing or voltage conditions of a pin driver, require that the test system be placed into a wait state while the pin's condition is reprogrammed. In test programs of typical complexity such pin reprogramming occurs many times during the test program. As a result, the time delay incurred for each system wait state is incremental, resulting in a significant throughput loss.
Furthermore, a general purpose test system for VLSI must be capable of efficiently testing, at the chip or the module level, sequential and combinatorial logic, storage arrays such as Read Only Memory (ROM), and Random Access Memory (RAM) arrays embedded in logic. In that VLSI chips containing logic are preferably designed with Level Sensitive Scan Design (LSSD) shift register techniques to enhance testability, the ability to test embedded memory and also LSSD structures must be supported by the test system.
Also, for very high levels of integration or for multi-chip modules the number of data vectors (X) that are required to test the product with a high level of test coverage becomes large. To eliminate the need to generate, transport/transmit, and store this large quantity of data, Weighted Random Pattern (WRP) testing with signature analysis at the DUT output pins is employed. WRP testing is described by J. A. Waicukauski and E. Lindbloom in "Fault Detection Effectiveness of Weighted Random Patterns", Proceedings of International Test Conference, 1988, pp. 245-249. As such, the provision of a test system that readily implements both deterministic and WPR testing is desirable.
In a journal article by C. W. Branson, "Integrated Pin Electronics for a VLSI Test System", IEEE Transactions on Industrial Electronics, Vol. 36, No. 2, May 1989, pp. 185-191 there is described test pin electronics circuitry. A 256.times.4 pattern memory is said to exist for each tester pin. In a journal article "High Performance Gate Array", High Performance Systems, January 1989, W. Damm describes a verification tester that is said at page 62 to include 16-word register files for storing timing information that is changed on a vector-by-vector basis. In a description of a Megaone VLSI Test System (undated) each test pin is said to have 64 independent waveforms selected on the fly.
In U.S. Pat. No. 4,775,977, Oct. 4, 1988, entitled "Pattern Generating Apparatus", Dehara discloses a pattern generator for testing integrated circuit devices. A pattern memory 1A has a two bit output applied to both a driver pattern generator 1C and an expected pattern generator ID. When an output of an IO memory 1B is a logic "1" the driver pattern generator generates a combination of waveforms in dependence on the two bit output from pattern memory 1A. When an output of the IO memory 1B is a logic "0" the expected pattern generator 1D decodes the two bit output to generate an expected pattern. This technique is said to allow a driver pattern having a waveform corresponding to a given combination of different waveforms to be generated in synchronism with a timing signal and to also simplify testing the integrated circuit for a high impedance output condition. However, this teaching of Dehara appears to be limited to interconnections made between units normally associated with pattern generating devices. As a result, the teaching of Dehara does not alleviate, either singularly or in combination with the other references set forth above, the problem of specifying a large number of pin-states or pin-conditions, such ac formats, edge timing, driver voltage levels, receiver threshold levels and receiver strobe timing on a per-pin, per cycle, basis with a relatively small number of readily implemented interconnections made between a pattern generator module and a pin electronics module.
It is therefore an object of the invention to provide a true per-pin test system wherein a selectable number of N bits are employed to precisely control signals applied to a DUT and to precisely specify signal states expected to be received from a DUT.
It is another object of the invention to provide a true per-pin test system that eliminates a requirement that the system be placed in a wait state in order to change a pin format or other condition during a test in that a large number of pin states are preprogrammed into the tester prior to the test, with the changes of state occurring on the fly during testing.
It is a further object of the invention to provide a true per-pin test system that readily accommodates additional pin drive and/or receive functionality by increasing a width of a pin function control word generated from a relatively few and fixed number of signal lines provided from a test pattern generator.
It is a further object of the invention to provide a true per-pin test system having a large number of programmable pin states for efficiently testing embedded memory arrays and also LSSD structures, the test system readily accommodating both deterministic and WRP test methodologies.